This invention is related to semiconductor integrated circuits having connection pads (pads for external connections) arranged over active elements.
Connection pads are often used for probing during testing of a semiconductor integrated circuit. Connection pads are also used for wire bonding when assembling the semiconductor integrated circuit. Previously, the connection pads were not arranged over an active element-forming area where active elements such as transistors are formed, in order to prevent the active elements from being damaged by the mechanical stress applied for the bonding and/or probing.
However, the need for miniaturization of the elements increases the number of functions implemented in a semiconductor integrated circuit; and also increases the required number of connection pads to be placed on the semiconductor integrated circuit. Therefore, it may be highly desirable to reduce the chip area of the semiconductor integrated circuit by arranging the connection pads over the active elements.
For example, U.S. Pat. No. 6,232,662 (Patent Document 1), which is hereby incorporated by reference in its entirety, proposes to arrange a bonding pad over the active integrated circuit region by providing a conductive reinforcing structure that includes a grid-shaped metal wiring pattern below the bonding pad.
As explained above, connection pads may also be used, before they are used for wire bonding, for probing by probing needles. The probing needle often damages the surface of the pad during the probing, and the damage on the surface of the pad may cause failure of the bonding.
For example, Japanese Laid-open Patent No. 2000-164620 (Patent Document 2), which is hereby incorporated by reference in its entirety, proposes a countermeasure for this problem. That is, Patent Document 2 proposes to form the pad in a rectangular shape and to divide it in two portions, one for bonding and one for probing.
It may be possible to arrange connection pad, which is divided into a bonding area and a probing area, as proposed by Patent Document 2, over the active elements, as proposed by Patent Document 1. Thereby, it would be possible to prevent bonding failure and to reduce the area of the chip.
However, even with an advanced manufacturing process that permits the use of a large number of wiring layers, the utilization rate of the wiring layers, or the utilization rate of the wiring resources provided by the wiring layers, may be significantly lowered if the reinforcing structure uses many of the wiring layers. As a result, it becomes difficult to arrange a number of wires necessary to realize the logical function of the integrated circuitry under the connection pad. In fact, a conventional I/O circuitry that was not designed to be arranged under a connection pad may utilize a significant number of wiring layers. Such conventionally designed I/O circuitry generally cannot be placed under the connection pad.